Test MP+dmb.sy+[fr-rf]-addr-rfi-pos

AArch64 MP+dmb.sy+[fr-rf]-addr-rfi-pos
"DMB.SYdWW Rfe FrLeave RfBack DpAddrdW Rfi PosRR Fre"
Cycle=Rfi PosRR Fre DMB.SYdWW Rfe FrLeave RfBack DpAddrdW
Relax=
Safe=Rfi Rfe Fre PosRR DMB.SYdWW DpAddrdW [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe FrLeave RfBack DpAddrdW Rfi PosRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#2   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2        |             ;
 MOV W2,#1   | MOV W4,#1           |             ;
 STR W2,[X3] | STR W4,[X5,W3,SXTW] |             ;
             | LDR W6,[X5]         |             ;
             | LDR W7,[X5]         |             ;
Observed
    y=1; x=2; 1:X7=1; 1:X6=1; 1:X2=0; 1:X0=2;
and y=1; x=1; 1:X7=1; 1:X6=1; 1:X2=0; 1:X0=2;
and y=2; x=1; 1:X7=1; 1:X6=1; 1:X2=0; 1:X0=1;
and y=1; x=1; 1:X7=1; 1:X6=1; 1:X2=0; 1:X0=1;